ASICs for FRIB

Historically, analog signal processing systems have been large and cumbersome, but the production of ASICs for analog signal processing has proved to be a cost-effective solution for creating large channel-count (100’s and up) detector systems. Aside from those for TPC’s, the SIUE-WUSTL effort, reviewed in this talk, is the sole effort in the US invested in making ASICs for use at FRIB. Two new versions of existing chips and one new chip are currently under design and/or production. The most recent HINP ASIC, widely used for modest-to-large arrays of Si detectors, provides two active gain ranges but does not allow an external charge-sensitive (pre)amplifier (unlike the previous version). The next version will return the external CSA option, retain the dual-gain shapers and be compatible with a dual-gain CSA ASIC designed at RIKEN. A second, and greatly improved, PSD ASIC – with three gated integrators per channel - has been designed and fabricated and the support electronics are currently being upgraded. A 16-ch CFD ASIC has been designed and will be fabricated in 2018. The PSD+CFD chips are designed to work together to allow for large channel count arrays of scintillators with n/$\gamma$ or charged-particle differentiable signal forms.