A streaming readout DAQ system for the BDX experiment

The electronic board presented in this work is a 12-channel digitizer designed for Beam Dump eXperiment at JLab. Main features are a low cost per channel, a flexible and high-performance timing system, an adequate memory buffer, a versatile front-end circuitry, and a trigger-less approach.

The digitizing chain is based on a dual-ADC family, whose members are pin to pin compatible with a choice of 12/14 resolution bits and sampling frequencies from 65 to 250 MHz. For time alignment to a common reference, the board implements a White-Rabbit interface but also accepts a clock signal, which is jitter cleaned and distributed by a PLL. Physics data transmission and board control are accomplished by a commercial System-on-Module mezzanine board based on a Zynq7045.

The board applies a “level-0 trigger”, ie selects hits passing a programmable threshold; samples plus timestamp and channel information are coded in packets and forwarded to PCs for trigger selection and event building. The trigger-less paradigm simplifies both the hardware requirements and the data flow, moving the complexity of higher-level triggers toward the PC farm. The proposed algorithm is effectively scalable to adapt to whatsoever channel number, provided that the interconnection network needs to grow accordingly.