The ETROC Project: ASIC Development for CMS MTD Endcap Timing Layer (ETL) Upgrade

The Endcap Timing Readout Chip (ETROC), being developed for the CMS Endcap Timing Layer (ETL) for high luminosity LHC (HL-LHC), is presented. Each endcap will be instrumented with a two-disk system of MIP-sensitive LGAD silicon devices to be read out by ETROCs for precision timing measurements with time resolution down to 30 ps level. The ETROC is designed to handle a 16×16 pixel cell matrix, each pixel cell being 1.3$\times$1.3 mm$^{2}$ to match the LGAD sensor pixel size. The design of ETROC as well as prototype testing results are presented.