Smart Pixels: Algorithm design and hardware testing for a 28m ROIC for future pixel trackers

Disentangling the enormous number of particles produced at high energy colliders calls for cutting-edge silicon pixel detectors. These tracking detectors reconstruct the paths of charged particles, an essential experimental task. With billions of readout channels and event rates as high as 40 MHz, these detectors will generate petabytes of data per second. New technologies are needed for ultrafast and power-efficient data extraction. We show here work to design a readout integrated circuit (ROIC) with an on-chip machine learning (ML) algorithm to perform data reduction at the source. This work highlights the algorithm and hardware co-design, giving insight for a future 28nm ROIC implementation.