Prototyping a Global Common Module for the ATLAS Phase II TDAQ Upgrade

The High Luminosity Large Hadron Collider (HL-LHC) is fast approaching and promises to deliver a factor of six times more data than was previously collected by the LHC. To cope with the harsh radiation environments and large data rates, the ATLAS detector is undergoing upgrades, including a new ATLAS trigger system. This system will consist of a new Level 0 (L0) hardware and Event Filter software-based system. The upgraded L0 will include 54 common hardware platforms known as Global Common Modules (GCM's). Each GCM will use high performance electronics with two large field programmable gate arrays (FPGA's) to receive and process data from the muon and calorimeter subsystems. The work presented here details thermal and power consumption studies conducted at Brookhaven National Lab to evaluate design readiness and FPGA architecture choices. Also presented here is ongoing work on the development of a live monitoring system and production ready testing application.