Stacked 2D Materials For Temporal Gating of Ion Transport Through Nanopores with both DC and AC Gate Voltage

POSTER

Abstract

Transport properties of nanopores can be controlled by chemical modification, electrolyte conditions, or placing a gate near or in the pore, but with most systems changes are slow and allow a electrical double-layer (EDL) to form. Here, we present a nanopore system with 2D gates whose electrical potential is gated with DC or AC voltages. We drilled single sub-10nm nanopores by TEM in stacked 2D materials (hBN and graphene) over a 3um diameter micropore in a silicon nitride membrane. We tested hBN-graphene-hBN stacks, a ~3nm conducting layer of graphene between two insulating hBN flakes. We were then able to measure ionic current through the pores with varying KCl concentration using a PDMS conductivity cell. We also developed a thin printed circuit board (PCB) to apply high frequency voltages to the chip, and added metal electrodes to the chip with contacts to the graphene layer of an hBN-graphene-hBN stack. We then apply both DC and AC voltages to the electrodes, allowing us to test non-equilibrium EDL gating.

Presenters

  • Matthew Schiel

    University of California, Irvine

Authors

  • Matthew Schiel

    University of California, Irvine

  • Ethan Cao

    University of California, Irvine

  • Aaron H Barajas-Aguilar

    University of California, Irvine

  • DaVante Cain

    University of California, Irvine

  • Javier D Sanchez-Yamagishi

    University of California, Irvine

  • Zuzanna S. Siwy

    University of California, Irvine