High Performance Silicon Nanowire Field Effect Transistor

We report the fabrication and characterization of double-gated Si nanowire field effect transistors with excellent electrical characteristics and a small subthreshold slope: $\sim $ 85 mv/dec. The Si nanowires were grown by chemical vapor deposition at pre-defined location on a 50 nm thermal SiO$_{2}$ (bottom gate oxide). The source/drain electrodes (Al) were formed by using photolithographic alignment and metal lift-off processes. The nanowires were then covered with HfO$_{2}$ via atomic layer deposition. A thin layer of SiO$_{2}$ was deposited on the HfO$_{2}$ as a buffer layer before the top gate electrode formation (Al, using photolithographic and lift-off processes). This self-aligned process enables the integration of a large number of high-quality nanowire transistors for electronic circuitry. We have investigated the effect of device structure and annealing conditions on the final device performance, and developed theoretical models to assist the device optimization.