One-dimensional semiconductors for low-power electronic applications

Power dissipation is rapidly increasing from one to the next generation of silicon CMOS based chips. While following the ideal scaling rules should improve the performance without significantly increasing the power consumption, in particular the supply voltage has not been reduced in the past as required. Since the gate oxide thickness (SiO(N) in common CMOS applications) on the other hand has been decreased substantially, gate leakage currents have become a severe problem when the transistor is turned off. For logic applications, part of the applied voltage is used to switch the device from its off-state into its on-state while the other portion is used to drive the transistor into a regime of high transconductance. When asking the question about how to decrease the supply voltage to reduce power consumption of the device, both states have to be taken into account. Considering that currently more than 3 orders of magnitude current change are required to ensure proper circuit operation, already around 200mV of the supply voltage are used towards driving the transistor from the off-state to the on-state. This is true for charge-based devices that control current transport by means of a gate dependent barrier that can only be overcome by thermal emission. Those types of devices are characterized by an inverse subthreshold slope larger than around 60mV/dec. Altering the logic state by applying smaller voltages is highly desirable. My presentation will elucidate on the possibility of using band- to-band tunneling in carbon nanotubes as a viable approach to address both of the above aspects -- the transistor off- and on- state performance. I will use the example of carbon nanotube based devices to discuss various switching concepts in these low-dimensional geometries and to argue why a certain device structure should be favored over another.