Near-Interface Defects in SiO$_{2}$/SiC MOS Devices

The implementation of SiO$_{2}$/SiC MOSFETS for high power applications has been hindered by the high density of near-interface states. We have developed a method to distinguish both the energy and spatial distribution of defect states near insulator-semiconductor interfaces through a comparison of the thermal emission energy extracted from constant capacitance transient spectroscopy (CCDLTS) measurements and the interface Fermi energy (F$_{P})$. The dependence of F$_{P}$ on trap filling voltage at the CCDLTS peak temperature is determined from temperature-dependent 1MHz C-V curves. Capture by tunneling into oxide traps is detected in 4H- and 6H-SiC capacitors fabricated by oxidation followed by NO-annealing, with the difference in thermal emission energies consistent with the conduction band offsets of the two polytypes at the SiO$_{2}$/SiC interface. Comparison with results from first principles calculations suggests that the observed oxide traps are C$_{O}$=C$_{O}$ and interstitial Si [1]. SiC defects having energies close to the SiC conduction band are suggested to be carbon di-interstitial defects, (C$_{2})_{i}$, introduced during standard oxidation [1]. Well-known traps introduced in SiC by ion-implantation are observed in 4H-SiC MOS capacitors fabricated by N-implantation followed by standard oxidation, thus validating this new method [2]. \begin{enumerate} \item A.F. Basile, \textit{et al}., J. Appl. Phys. \textbf{109}, 064514 (2011) \item A.F. Basile, \textit{et al}., J. Appl. Phys. \textbf{109}, 114505 (2011). \end{enumerate}