Fabrication of sub-20 nm metal lines on Si substrates

As line width decreases below 15 nm, the diffusion barriers used in copper (Cu) technology in high performance integrated circuits significantly increase the overall resistivity of interconnects. In this work, we argue that the performance of pure W and Mo lines with line widths smaller than 15 nm could be better than that of Cu lines with barriers. We, herein, present a process of creating Cu, W and Mo metal nanolines on Si substrates using the combination of e-beam lithography (SUPRA 55 Scanning electron microscopy), oblique angle deposition, and lift-off techniques. The integrity of the sub-15 nm nanolines, including the line edge roughness, will be quantified. We shall also report our attempts to measure the resistivity of these nanolines using four point probe techniques. The relative contributions of phonon scattering versus surface scattering will be discussed. The effect of line edge roughness to the overall resistivity will also be presented.