Tuning the gate efficiency in epitaxially grown InGaAs-InAs heterostructures

Fabrication of gate-defined devices on epitaxially grown heterostructures containing InAs layers is highly desirable as it offers the possibility of tuning the confinement potential, carrier density and spin orbit coupling. However, reliable gating has proven difficult in these materials due to gate leakage and hysteretic behavior. In addition, charge traps and Fermi level pinning could screen the applied electric field and significantly reduce the gate efficiency. In this work, we have studied the effect of surface gating on epitaxially grown In$_{0.75}$Ga$_{0.25}$As-InAs-In$_{0.75}$Ga$_{0.25}$As quantum wells. We find that the application of the gate bias barely changes the carrier density and the efficiency of the gate to be poor. However when a positive voltage is applied to the gate during cool down, the gate efficiency is improved. Furthermore, the change in density as a function of gate bias becomes linear and the slope matches closely to the simple capacitance model. We have also fabricated a quantum point contact using a split gate design on a similar structure and achieved full depletion under the gates. The conductance plot as a function of side gate voltages shows quantized plateaus reminiscent of ballistic one-dimensional transport.