Fabrication of Ultra-low-contact-resistance Graphene Devices

Reactive graphene surface is important to facilitate carriers transport from graphene to other contacting material or vice versa. In this work, we present a technique that is both simple and complementary metal-oxide-semiconductor (CMOS) compatible to generate a significant amount of nano-sized pores in the graphene surface. Edge termination of the created pores in graphene was verified to be of pure zigzag configuration. A number of graphene field-effect transistors were fabricated such that the graphene channel remained intact and the graphene under metal contacts were made porous. These graphene devices exhibit very low contact resistance which is about 60{\%} better than that required for the silicon-based technology at 22 nm node with much higher mobility. In addition, approaches to control the size of pores created in graphene down to sub-nanometer regime and their density will be discussed. In short, the findings suggest that the creation of well-defined nanopores in graphene could be a promising method to enhance interaction of graphene with the contacting metal and thus optimizing the performance of graphene devices.