Understanding the physics that causes hysteresis in carbon nanotube transistors, a key step toward high performance and energy-efficiency

Three-dimensional (3D) integration is a promising technology that achieves higher energy efficiency, higher performance, and smaller footprint than today's planar, 2D technology [1]. In particular, carbon nanotube field-effect transistors (CNFETs) enable monolithic 3D integration due to its low-temperature processing (\textless 400 $^{\circ}$ C) [2]. Although CNFETs promise high-performance and energy-efficient digital systems, large hysteresis has long remained a challenge. Our approach to eliminating hysteresis is based on our understanding of the physics that lead to hysteresis [3]:\\ \\Understanding the sources of hysteresis: We develop a novel measurement technique called the Pulsed Time-Domain Measurement (PTDM) which enables quantification of charged traps responsible for hysteresis. Leveraging a physics-based model, we study the mechanism of the charge trapping process.\\ \\Eliminating hysteresis: After gaining a deeper understanding of the sources of hysteresis, we are able to develop a VLSI-compatible, solid-state fabrication method that mitigates the effect of traps. On average, we achieve hysteresis of less than 0.5{\%} of the gate-source voltage sweep range. \newline \newline Reference: \newline [1] M.M. Sabry Aly, M. Gao, G. Hills, C.-S. Lee, G. Pitner, M.M. Shulaker, T.F. Wu, M. Asheghi, J. Bokor, F. Franchetti, K.E. Goodson, C. Kozyrakis, I. Markov, K. Olukotun, L. Pileggi, E. Pop, J. Rabaey, C. Re, H.-S. P. Wong, S. Mitra, "Energy-Efficient Abundant-Data Computing: The N3XT 1,000X," IEEE Computer, pp. 24 -- 33, December 2015\newline [2] M. Shulaker, T. Wu, A. Pal, K. Saraswat, H.-S. P. Wong, S. Mitra, ``Monolithic 3D Integration of Logic and Memory: Carbon Nanotube FETs, Resistive RAM, and Silicon FETs,'' IEEE International Electron Devices Meeting (IEDM), paper 27.4, pp. 638 -- 641, December 15 -- 17, San Francisco, 2014 \newline [3] R. S. Park, M. M. Shulaker, G. Hills, L. S. Liyanage, S. Lee, A. Tang, S. Mitra, H.-S. P. Wong, "Hysteresis in Carbon Nanotube Transistors: Measurement and Analysis of Trap Density, Energy Level, and Spatial Distribution," ACS Nano 10, pp. 4599 -- 4608, March2016