Optimizing gates in the presence of leakage errors

As coherence times of superconducting transmon qubits improve, leakage errors become an important error source that must be taken into account for the design of high fidelity gates, and for achieving fault tolerance thresholds in surface code protocols. We discuss methods for quantifying and characterizing leakage errors in quantum gates, and show how these relate to standard measures of average gate fidelity from randomized benchmarking. We also compare methods for achieving low-leakage, high fidelity single qubit gates by using alternative techniques to standard DRAG control pulses.