Charge offset drift in silicon-on-insulator mesa-etched single electron devices with Al gates

Charge offset drift in single electron devices (SEDs) deleteriously affects their applications in metrology and quantum computing by complicating integration of devices. Our recent measurements on single-layer SEDs show that the charge offset drift not only depends on the material system, but also depends on the device design.[1] This result prompts us to revisit silicon-on-insulator (SOI) mesa-etched SEDs. Previous results show that the charge offset drift is minimal in SOI devices with a polySi/SiO₂/Si gate stack (ΔQ₀<0.01e),[2] while devices made on bulk wafers with an Al/SiO₂/Si gate stack show higher levels of drift (ΔQ₀~0.15e). [3] In this work, we keep the device geometry and structure of the SOI devices but modify the gate stack to be Al/SiO2/Si. We will present the charge offset drift results on these SOI mesa-etched SEDs with Al gates. The individual roles being played by the material system and the device structure in determining the level of charge offset drift will be discussed.
[1] Binhui Hu, Neil M. Zimmerman and M. D. Stewart, Jr., in preparation.
[2] N. M. Zimmerman, B. J. Simonds, A. Fujiwara, Y. Ono, Y. Takahashi, and H. Inokawa, Appl. Phys. Lett. 90, 033507 (2007).
[3] N. M. Zimmerman, C. H. Yang, N. S. Lai, W. H. Lim and A. S. Dzurak, Nanotechnology 25 405201