Impact of gate-induced strain on silicon MOS quantum dot tunnel barriers

Gate defined quantum dots in silicon are extremely sensitive to disorder in the local environment of the quantum dot. In the Si MOS system, disorder can originate from oxide charge defects, substrate impurities, and strain. One significant source of inhomogeneous strain in silicon quantum dots is induced by the gate materials. This strain originates in the intrinsic stress in the gate material as deposited and differences in the thermal properties between the gate and substrate. At low temperatures, this strain leads to local modifications of the conduction band strong enough to form unintentional quantum dots and to affect the tunnel coupling between dots. In this work, we investigate the role of gate-induced strain by comparing measurements of the 4-terminal I-V characteristics of tunnel barrier devices at 2K. The devices are fabricated on bulk silicon wafers with Al and poly-silicon gate electrodes separated by tunnel gap lengths ranging from 20-40nm and gate widths ranging from 50 to 500 nm. Using a WKB tunnel barrier model, we find that Al gates devices have on order of 1 meV larger barrier heights as compared to poly-silicon devices when the extracted barrier width is about 30 nm. We will discuss these results in terms of the strained induced modulation of the barrier.