CMOS compatible processing for phosphorous delta-layer nanoscale electronics

Silicon based phosphorous delta layer electrical devices are a potential pathway to high efficiency transistors. A widely known fabrication path involves scanning tunneling microscope (STM) based hydrogen lithography. We present a low temperature STM sample preparation that enables significant processing of devices prior to STM. This preparation enables a CMOS compatible fabrication path that scales from the nanoscale STM patterned device to macroscopic bond pads using only optical lithography. Using low-temperature electrical transport, we demonstrate a high yield of delta-layer based, nanoscale electrical devices across numerous fabrication runs. This work was supported by the Laboratory Directed Research and Development Program at Sandia National Laboratories, and was performed, in part, at the Center for Integrated Nanotechnologies, a U.S. DOE, Office of Basic Energy Sciences user facility.

Sandia National Laboratories is managed and operated by National Technology and Engineering Solutions of Sandia, LLC., a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy under contract DE-NA-0003525.