Floating gate memory based on ion-insertion electrodes for low-voltage analog computing
ORAL
Abstract
A major barrier to realizing neuromorphic hardware is development of analog memory with the programmability and the energy efficiency to compete with conventional hardware. On one hand, CMOS-based floating gate memory (FGM) such as NAND Flash has large programming voltages (>8V) that limits array-level energy efficiency. On the other hand, memristors suffer from non-linear resistance levels and device variability that limit neural network accuracy. To overcome these challenges, we introduce ionic floating-gate memory (IFG). Similar to FGM, IFG is programmed via voltage pulses to a control gate which modulates the doping of a semiconducting channel. However, unlike CMOS, which relies on hot carrier injection or tunneling through an oxide, IFG relies on ion-exchange through a solid electrolyte. Resistance switching occurs as ions are inserted into the channel from the floating gate. The use of a diffusive memristor as the control gate allows for programming pulses < 500 mV, while maintaining the retention required for learning. In addition, the devices can be tuned to >100 resistance levels with a linear response ideal for neural algorithms. Neural network simulations of the device performance are found to reach ideal accuracy when classifying MNIST hand-written digits.
–
Presenters
-
Albert Talin
Sandia Natl Labs
Authors
-
Elliot Fuller
Sandia Natl Labs
-
Scott Keene
Stanford
-
Zhongrui Wang
University of Massachessetts, Amherst
-
Sapan Agarwal
Sandia Natl Labs
-
Francois Leonard
Sandia National Laboratories, Sandia Natl Labs
-
Yang Joshua
University of Massachessetts, Amherst
-
Matthew Marinella
Sandia Natl Labs
-
Alberto Salleo
Stanford
-
Albert Talin
Sandia Natl Labs