Effect of varying the gate voltage scan rate in a MoS₂/ferroelectric polymer field effect transistor

A ferroelectric field effect transistor (FE-FET) using chemical vapor deposition (CVD) grown monolayer MoS₂ as the semiconductor was fabricated and tested at room temperature. Ferroelectric poly(vinylidene fluoride-trifluoroethylene)-PVDF-TrFE was used as the gate insulator, and the effects of varying the gate voltage scan rate from 200 mV/s to 4 mV/s on device performance were investigated. Prior to the device switching on, a negative trans-conductance was observed for all scan rates. It was followed by a rapid increase in the channel current to the on state, corresponding to the polarized down configuration of the FE. This effect was independent of the drain-source voltage. Our results revealed a narrowing in the memory window width, an increase in the mobility (μ) from 0.02 – 10 cm²/V-s, and a decrease in the sub-threshold voltage swing (SS) as the scan rate was lowered. These parameters appeared to stabilize at slower scan rates suggesting an asymptotic limit to their values. A model based on nucleation and unrestricted domain growth was used to explain these results. By lowering the gate voltage scan rate, the performance of polymer based FE-FET’s can therefore be improved.