Spin Qubits at Intel

Intel is developing a 300mm process line for spin qubit devices using state-of-the-art immersion lithography and isotopically pure epitaxial silicon layers. Both Si-MOS and Si/SiGe devices are being evaluated in this multi-layer integration scheme. In this talk, we will be sharing our current progress towards spin qubits starting with substrate characterization. Transistors and quantum dot devices are then co-fabricated on the same wafer and allow calibration to Intel’s internal transistor processes. Electrical characterization and feedback is accomplished through wafer scale testing at both room temperature and 1.6K prior to milli-kelvin testing. Accelerated testing across a 300mm wafer provides a vast amount of data that can be used for continuous improvement in both performance and variability. This removes one of the bottlenecks towards a large scale system: trying to deliver an exponentially fast compute technology with a slow and linear characterization scheme using only dilution refrigerators.