Limits to Charge Carrier Motion in High-Performance Organic Semiconductors: Role of Energy Barriers at Grain Boundaries and Interface Traps

Using our recently developed surface-crystallization method [1], we have realized 3 – 10 nm thin, highly-crystalline thin films or a novel perylene diimide and investigated temperature-dependent charge transport. Via a combination of as-measured density-of-states with Kinetic Monte Carlo simulations [2], we present strong hints that it is rather the energetic barriers at grain boundaries than the usually identified energetic traps that limit charge carrier motion below room temperature. We furthermore have observed that above room temperature the charge carrier mobility decreases upon increasing the charge carrier density in the semiconducting film [3]. While the true cause for this suppression is currently unclear, we present evidence that the squeezing of charges closer to the semiconductor/dielectric by the gate dielectric field a subsequent scattering at this interface might cause the drop in mobility. We believe that our combined observations will help to understand the still debated nature of charge transport in high-quality organic semiconductors.

[1] I. Vladimirov et al. Nano Letters 18, 9, (2018)
[2] I. Vladimirov et al. Scientific Reports 8, 14868, (2018)
[3] I. Vladimirov et al, in preparation