Scaling the input/output architecture of quantum processors to kQbit, and beyond, size in the NISQ era

Most quantum computing hardware architectures combine the requirements of individually addressable qubits and cryogenic temperatures of the quantum processor. This combination makes the design of the interface between the quantum processor and its classical backend a critical element in the scalability of the architecture of the quantum computer. Todays coaxial cabling solution becomes (at best) impractical for processors beyond the kQbit regime, due to its unwanted resonances, form-factor, costs and thermal load. Moreover the non-uniformity of the individual lines complicates the operation and control of the quantum processor by its classical back-end. Here we discuss an input/output (i/o) system for scalable quantum computers that uses a monolithic multi-layer flexible circuit from room temperature to ~10 miliKelvin to interface the quantum processor with its room temperature electronics. Important aspects like thermal properties, signal transmission and conditioning by integrated filtering, and cross-talk are reviewed for the various approaches to quantum computing. Also the required modularity and inter-operability of the cryogenic hardware and interface to the quantum processor are considered.