Ternary and higher order classical cryogenic memory cells

For many classical cryogenic computing applications, a key issue in designing powerful and practical systems is the scaling of memory. In particular, the amount of circuitry required to build and access memory units has limited the amount of information that it is possible to store. A possible solution to this problem is to consider designs that store more information in a single memory unit. Therefore, it may be beneficial considering ternary and higher order multivalued memory systems that use the same number of Josephson junctions as binary units.

In this talk we will present a ternary cryogenic memory cell paradigm based on an array of inductively coupled Josephson junctions[1]. We show how reading, writing and resetting are implemented using single flux quantum (SFQ) current pulse inputs and outputs from the circuit. We further show how both destructive readout (DRO) and nondestructive readout (NDRO) can be implemented.

1. N. Nair and Y. Braiman, Supercond. Sci. Technol. 31, 115012 (2018).