Dielectric Conduction in the Post-breakdown Region Predicted Using a Charge Transport Model

A Charge Transport Model was developed originally in our group to predict time-dependent dielectric breakdown (TDDB) in the back end of line (BEOL) interconnects. Both ramped voltage stress tests (RVS) and constant bias stress tests (CVS) data could be simulated with a same set of fitting parameters by the model.

To investigate what happens post-breakdown, we removed the industrially defined breakdown condition that was used to stop the simulation and with adjustments to the voltage response of both the Schottky barrier height and of the electron at the metal/dielectric interface, the model has now been extended into the post-breakdown region. The revised model can now predict the entire current vs. time history from the breakdown to ohmic behavior post-breakdown.

The linear I-V behavior agrees with the experimental observations of the current behavior of various resistive random-access memories (ReRAM) at low resistive state (LRS) after the generally required ‘Forming’, which is essentially a dielectric breakdown process. The extended charge transport model, therefore, provides a possible explanation for the ReRAM conduction mechanism at LRS by treating it as an incompressible electronic flow system.