Ferroelectricity-induced negative capacitance in microelectronic devices via phase-field simulations and machine learning
ORAL
Abstract
* This work was supported by the US Department of Energy, Office of Science, Office of Basic Energy Sciences, the Microelectronics Co-Design Research Program, under contract no. DE-AC02- 05-CH11231 (Codesign of Ultra-Low-Voltage Beyond CMOS Micro-electronics) for the development of design tools for low-power microelectronics. This research used resources of the National Energy Research Scientific Computing Center, a DOE Office of Science User Facility supported by the Office of Science of the U.S. Department of Energy under Contract No. DE-AC02-05CH11231. This research leveraged the open-source AMReX code, https://github.com/AMReX-Codes/amrex. We acknowledge all AMReX contributors. The authors thank Lane Martin, Thomas Lee, Raul. A. Flores, Jack Broad, Sinéad Griffin, and Ramamoorthy Ramesh for valuable discussions.
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Publication: Design of NCFET Gate Stack with Machine Learning (planned paper).
Presenters
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Christian A Fernandez
University of Texas at El Paso
Authors
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Christian A Fernandez
University of Texas at El Paso
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Jorge A Munoz
University of Texas at El Paso
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Yadong Zeng
Altair Engineering Inc.
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Prabhat Kumar
Lawrence Berkeley National Laboratory
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Andy J Nonaka
Lawrence Berkeley National Laboratory
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Zhi (Jackie) Yao
Lawrence Berkeley National Laboratory