multi-scale simulation framework for calculation of charge noise induced dephasing time of hole spin qubits in Si FinFETs

Spin qubits based on Si CMOS devices are great candidates to build large-scale quantum processors. In these devices, charge noise can be a major source of qubit dephasing. Here, we present a simulation framework that is capable of calculating the qubit’s dephasing time T₂^* at 1K and use a recently reported hole spin qubit in a Si FinFET to test it [1]. To obtain T₂^*, we implemented the theoretical model of [2]. It requires as inputs the potential fluctuation induced by charge noise and the g-tensor at the qubit’s location.

Sentaurus Device is employed to compute the potential fluctuation, which is assumed to be related to the displacement of SiO₂/Si interface traps. A total of 300 random trap locations is considered. For each of them, we run two sets of DC simulation, one where the traps are located directly at the SiO₂/Si interface and one where they are displaced into SiO₂ by 5 Å. We then extract the induced potential change from these distinct runs. The final potential fluctuation is found by taking the root mean square of the 300 trap configurations.

A home-made Schrödinger-Poisson solver, QTSolver, is used to calculate the g-tensor. The qubit’s ground state is determined based on a 6x6 k•p Hamiltonian that automatically captures the mixing between the predominant heavy and light hole bands. Following the method introduced in [3], the degenerated qubit’s eigenvector pairs allow for the evaluation of the g-tensor.

The results of Sentaurus Device and QTSolver are finally post-processed to produce T₂^*.

[1] L. C. Camenzind et al., Nat Electron 5, 178-183 (2022) [2] S. Bosco et al., PRX Quantum 2, 010348 (2021) [3] B. Venitucci et al., Phy. Rev. B 98, 155319 (2018)