Charge-parity switching effects and optimisation of transmon-qubit design parameters

Enhancing the performance of noisy quantum processors requires improving our understanding of error mechanisms and the ways to overcome them. A judicious selection of qubit design parameters, guided by an accurate error model, plays a pivotal role in improving the performance of quantum processors. In this study, we identify optimal ranges for qubit design parameters, grounded in comprehensive noise modeling. To this end, we commence by analyzing a previously unexplored error mechanism that can perturb diabatic two-qubit gates due to charge-parity switches caused by quasiparticles. We show that such charge-parity switching can be the dominant quasiparticle-related error source in a controlled-Z gate between two qubits. Moreover, we also demonstrate that quasiparticle dynamics, resulting in uncontrolled charge-parity switches, induce a residual longitudinal interaction between qubits in a tunable-coupler circuit. Our analysis of optimal design parameters is based on a performance metric for quantum circuit execution that takes into account the fidelity and frequencies of the appearance of both single and two-qubit gates in the circuit. This performance metric together with a detailed noise model enables us to find an optimal range for the qubit design parameters. Substantiating our findings through exact numerical simulations, we establish that fabricating quantum chips within this optimal parameter range not only augments the performance metric but also ensures its continued improvement with the enhancement of individual qubit coherence properties. Conversely, straying from the optimal parameter range can lead to the saturation of the performance metric. Our systematic analysis offers insights and serves as a guiding framework for the development of the next generation of transmon-based quantum processors.