Systems Architecture for Quantum Random Access Memory
ORAL
Abstract
Operating on the principles of quantum mechanics, quantum algorithms hold the promise for solving problems that are beyond the reach of the best-available classical algorithms. An integral part of realizing such speedup is the implementation of quantum queries, which read data into forms that quantum computers can process. Quantum random access memory (QRAM) is a promising architecture for realizing quantum queries. However, implementing QRAM in practice poses significant challenges, including query latency, memory capacity and fault-tolerance.
We propose the first end-to-end system architecture for QRAM. First, we introduce a novel QRAM that hybridizes two existing implementations and achieves asymptotically superior scaling in space (qubit number) and time (circuit depth). Like in classical virtual memory, our construction enables queries to a virtual address space larger than what is actually available in hardware. Second, we present a compilation framework to synthesize, map, and schedule QRAM circuits on realistic hardware. For the first time, we demonstrate how to embed large-scale QRAM on a 2D Euclidean space, such as a 2D square grid layout, with minimal routing overhead. Third, we show how to leverage the intrinsic biased-noise resilience of the proposed QRAM for implementation on either Noisy Intermediate-Scale Quantum (NISQ) or Fault-Tolerant Quantum Computing (FTQC) hardware. Furthermore, our architecture holds the potential to implement a low-overhead error correction scheme by taking advantage of the intrinsic redundancy in QRAM. Finally, we validate these results numerically via both classical simulation and quantum hardware experimentation.
We propose the first end-to-end system architecture for QRAM. First, we introduce a novel QRAM that hybridizes two existing implementations and achieves asymptotically superior scaling in space (qubit number) and time (circuit depth). Like in classical virtual memory, our construction enables queries to a virtual address space larger than what is actually available in hardware. Second, we present a compilation framework to synthesize, map, and schedule QRAM circuits on realistic hardware. For the first time, we demonstrate how to embed large-scale QRAM on a 2D Euclidean space, such as a 2D square grid layout, with minimal routing overhead. Third, we show how to leverage the intrinsic biased-noise resilience of the proposed QRAM for implementation on either Noisy Intermediate-Scale Quantum (NISQ) or Fault-Tolerant Quantum Computing (FTQC) hardware. Furthermore, our architecture holds the potential to implement a low-overhead error correction scheme by taking advantage of the intrinsic redundancy in QRAM. Finally, we validate these results numerically via both classical simulation and quantum hardware experimentation.
* Yongshan Ding acknowledges support from NSF (under award CCF-2312754) and Yale University. Steven M. Girvin was supported by the Air Force Office of Scientific Research under award number FA9550-21-1-0209.
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Publication: Arxiv: https://doi.org/10.48550/arXiv.2306.03242
56th IEEE/ACM International Symposium on Microarchitecture: https://doi.org/10.48550/arXiv.2306.03242
Presenters
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Shifan Xu
Yale University
Authors
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Shifan Xu
Yale University
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Connor T Hann
AWS Center for Quantum Computing
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Ben Foxman
Yale University
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Steven M Girvin
Yale University
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Yongshan Ding
University of Chicago