Investigating single- and two-qubits performances in superconducting quantum processors

The roadmap towards quantum computing requires building platforms with a sufficient number of qubits and gate/readout fidelity to achieve the quantum advantage. Among the most promising hardware, superconducting quantum platforms have earned considerable attention among the research community and leading industries in the field [1,2]. Their artificial nature favors the engineering of coherence [3], control and readout [4-5], and tunability [4,6-7], as well as coupling schemes for enhanced scalability [8,9]. Several governments and academic centers are considering pursuing their own quantum computer. In the frame of the Italian High-Performance Computing and Data Center (HPC), we report on the first experiments involving state-of-the-art single- and two-qubit protocols [10], as well as the implementation of single- and two-qubit quantum circuits on few-qubits processors performed by a public academic institution in Italy [11]. Towards quantum algorithms run on a scalable system with up to 30 transmon qubits by the end of 2024, we here report some first experimental validation of Quantum Error Mitigation (QEM) algorithms. Specifically, we have performed a proof-of-principle implementation on a 2-qubit register of a recently proposed QEM technique that uses Fuzzy C-Means (FCM) clustering to identify and mitigate measurement error patterns [11]. This prepares the field for new algorithms, and novel research routes in the field of superconducting quantum technologies and quantum information, involving an increasing number of qubits and complexity of the devices.

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[11] Ahmad et al., in preparation