Variability mitigation in epitaxial-heterostructure-based spin qubit arrays via gate layout optimization

The scalability of spin qubit devices may be compromised due to variability induced by disorder in the host materials. Charge traps, in particular, are particularly problematic due to their strong Coulomb interaction with the carriers of the qubits. In this sense, epitaxial heterostructures are of high interest given their low level of disorder at the vicinities of the active layer. The charge traps in these devices are indeed mostly located at the top GeSi/oxide interface, which is a few tens of nanometers away from the qubits. Their presence may still induce non-negligible inhomogeneities in the qubits chemical potentials and couplings, which complicates the management of spin qubit arrays.

In this work, we focus on hole qubits in Ge/SiGe heterostructures and simulate the impact of variability on the chemical potential, detuning, and tunnel coupling between qubit pairs in a prototypical 2D spin qubit array. We unveil the key role of gate coverage on screening the charge traps, and propose alternative designs to minimize the variability figures. These findings emphasize the importance of device design in enhancing resilience against interface traps and provide valuable insights in the quest for scalable spin qubit architectures.