Cryogenic Threshold Engineering in commercially available MOSFETs

Here we illustrate cryogenic threshold engineering by selecting a commercially avilable field effect transistor to minimise its threshold voltage at low temperature, reducing the necessary supply voltages for associated cryo-circuitry. We demonstrate DC characterisation of commercially available, low-voltage, FETs in the range 295K-1.5K, extracting key parameters such as subthreshold slope, threshold voltage and peak transconductance. We further demonstrate the applications of cryogenic threshold engineering by first simulating a common source amplifier and then cooling an amplifier designed with depletion mode n-type FETs. To quantify the improvement of in operation of the amplifier a Figure Of Merit (FOM), the ratio of Gain-Bandwidth-Product to power consumption is defined and measured in both simulation and experiment. We found in both simulation and experiment that an order of magnitude improvement in the FOM was attributed to the movement of the threshold voltage upon cooling. Whilst bellow 30K the FETs suffered from freeze-out, we believe this technique could be used to improve the power consumption of cryogenic electronics in areas such as quantum computing, where management of the thermal mode is critical.