Design and execution of quantum circuits using tens of superconducting qubits and thousands of gates for dense Ising optimization problems

We develop a hardware-efficient ansatz for variational optimization, derived from existing ansätze in the literature, that parametrizes subsets of all interactions in the cost hamiltonian in each layer. We treat gate orderings as a variational parameter and observe that doing so can provide significant performance boosts in experiments. We carried out experimental runs of a compilation-optimized implementation of fully-connected Sherrington-Kirkpatrick Hamiltonians on a 50-qubit linear-chain subsystem of Rigetti's Aspen-M-3 transmon processor. Our results indicate that, for the best circuit designs tested, the average performance at optimized angles and gate ordering parameters increases with circuit depth (using more parameters), despite the presence of a high level of noise. We report performance significantly better than using a random guess oracle for circuits involving up to ~5,000 two-qubit and ~5,000 one-qubit native gates. We additionally discuss various takeaways from our results toward more effective utilization of current and future quantum processors for optimization. The submission is based on preprint arXiv:2308.12423.