Demonstration of Real-Time Decoding in a Quantum Control Stack within 500 ns

The effectiveness of quantum error correction (QEC) is underpinned by the decoder, which in a universal fault-tolerant quantum computer has to run in real time, on an extremely tight schedule (e.g., microsecond timescale for superconducting qubits). So far, the QEC literature has predominantly focused on the QEC-code design and decoder accuracy. However, its real-time implementation is a critical milestone. First, real-time decoding requires a fast decoding algorithm running on suitable computational resources. A comprehensive review and perspective can be found in Battistel et al (arXiv:2303.00054). We identify the union-find Helios decoder by Liyanage et al (arXiv:2301.08419) as one of the most promising candidates. Second, real-time decoding requires communication of measurement results before the ones from the previous QEC cycle are generated, as well as low-latency communication of decoder outcome. In particular, to prove the feasibility of real-time decoding, it is necessary to demonstrate this using an FPGA (or ASIC) that is tightly integrated with the quantum control stack. While there have been previous implementations of standalone FPGA decoders, and numerous software decoders, there is a lack of demonstrations showcasing decoding within a quantum control stack. We adapt the union-find Helios decoder by Liyanage et al to run within 128 nanoseconds for a 3x3x3 surface code in an FPGA sequence processor and within 500 ns for the full round in the control stack. The decoding module is designed to seamlessly interface with the distributed communication network running over the backplane of the control system. This work is a milestone towards bringing real-time decoding to experimental reality. We envision a decoding platform to extend the available decoding set to other promising decoders.