Multi-FPGA Union-Find Decoder for Surface Codes

A fault-tolerant quantum computer must have an accurate and real-time quantum error correction decoder. For superconducting qubits, the decoder should have an average throughput of around 1 us per measurement round with minimal latency to prevent a backlog of measurements from accumulating. The distributed Union-Find (UF) decoder by Liyanage et.al (arXiv:2301.08419) is a promising candidate with a sublinear average time complexity with regard to code distance (d). However, the resource usage of the decoder grows O(d3log(d)), thus the available resources in a single FPGA limit decoding large surface codes or performing multi-logical qubit operations such as lattice surgery.

We map the Helios architecture proposed to run the decoder to a custom multiple-FPGA system with a hybrid tree-grid topology. We demonstrate for the first time a decoder that is not constrained by resources and can run across multiple FPGAs. We show the validity of the decoder design and the multi-FPGA system by decoding large surface code blocks with (d>20) lattice surgery faster than the rate of measurement. Given the prevalence of multi-FPGA systems in contemporary quantum control setups, we anticipate that our approach is a promising candidate for practical real-time QEC for fault-tolerant quantum computing.