Enhancing execution efficiency of quantum-classical algorithms through hardware-efficient implementation on FPGAs

The current era of quantum computing depends on classical computing for controls and hybrid algorithm implementation. However, relying on classical computations can hinder the realization of quantum advantages due to longer latency times, affecting the overall performance of hybrid algorithms. Additionally, classical computing platforms, such as FPGAs, are non-trivial design platforms that require domain expertise for efficient implementation. Thus, enhancing execution efficiency requires implementing flexible classical computational features within the agreeable latency budget.

Our work introduces an implementation of classical computation on FPGA control hardware, using a lean design approach to create digital circuits with minimal latency. Further, we incorporate digital elements to create a versatile architecture capable of supporting a variety of hybrid algorithms. To showcase the hardware-efficient efficacy of our approach, we profile with a parameter-shift application and measure the performance against other classical computations. We envision the success of this approach impacts the performance of hybrid algorithms, and we look forward to further exploring its potential.