Demonstrating High Performance, Ultra-Low Power with High Photoresponsivity of Van der Waals Transistors for Back-End-of-Line Machine Vision Applications
ORAL
Abstract
Recent work on machine vision (MV) devices have demonstrated the promise of 2D materials and devices hold. However, the scalability of 2D devices faces several challenges, including high contact resistance, Fermi Level Pinning (FLP), high power consumption, and low-cost fabrication lithography processes. To enable integration of CMOS with 2D materials, it is crucial to identify an appropriate lithography strategy that can meet these different requirements.
In this context, we investigate new lithography strategy identified under modified van der Waals (vdW) deposition method. We showcase a relatively novel 2D-FETs called van-der-Waals-Field-Effect-Transistors (vdW-FETs) based on 2D materials. This fabrication strategy empowers us to create high-performance devices, evident by a substantial current on-off ratio (Ion/Ioff), a high turn-on current density (Ion), and a reduced Fermi Level Pinning (FLP). We apply this method to show a gate-tunable near-ideal diode utilizing a MoS2/WSe2 heterojunction, which exhibits an ideality factor of approximately 1.65 and a high current rectification.
Furthermore, we demonstrate an exceptionally sensitive, scalable, and ultra-low power photodetector using MoS2/WSe2 vdW-FETs, designed for Back-End-of-Line (BEOL) integration. Our photodetector sets a new standard for gate-tunable photoresponsivity for white light detection, achieving ultra-low power consumption. This unique gate tunable photodetector based on MoS2/WSe2 vdW-FETs paves the way for ultra-sensitive, rapid, and efficient in-sensor machine vision. Our approach underscores the immense potential of modified vdW deposition lithography for Back-End-of-Line CMOS+2D.
In this context, we investigate new lithography strategy identified under modified van der Waals (vdW) deposition method. We showcase a relatively novel 2D-FETs called van-der-Waals-Field-Effect-Transistors (vdW-FETs) based on 2D materials. This fabrication strategy empowers us to create high-performance devices, evident by a substantial current on-off ratio (Ion/Ioff), a high turn-on current density (Ion), and a reduced Fermi Level Pinning (FLP). We apply this method to show a gate-tunable near-ideal diode utilizing a MoS2/WSe2 heterojunction, which exhibits an ideality factor of approximately 1.65 and a high current rectification.
Furthermore, we demonstrate an exceptionally sensitive, scalable, and ultra-low power photodetector using MoS2/WSe2 vdW-FETs, designed for Back-End-of-Line (BEOL) integration. Our photodetector sets a new standard for gate-tunable photoresponsivity for white light detection, achieving ultra-low power consumption. This unique gate tunable photodetector based on MoS2/WSe2 vdW-FETs paves the way for ultra-sensitive, rapid, and efficient in-sensor machine vision. Our approach underscores the immense potential of modified vdW deposition lithography for Back-End-of-Line CMOS+2D.
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Presenters
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Mohammed R Amer
King Abdulaziz City for Science and Technology, Department of Electrical Engineering, Henry Samueli School of Engineering, University of California, Los Angeles, CA, King Abdulaziz City Science & Technology (KACST), UCLA and USC
Authors
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Mohammed R Amer
King Abdulaziz City for Science and Technology, Department of Electrical Engineering, Henry Samueli School of Engineering, University of California, Los Angeles, CA, King Abdulaziz City Science & Technology (KACST), UCLA and USC