Improving algorithmic performance using hardware efficient gates

Useful quantum algorithms which utilize only the standard entangling gates like CNOT, iSWAP, etc. fail to produce meaningful results on the NISQ devices. Superconducting circuits provide a diverse variety of native multi-qubit interactions depending on the device architecture and gate-drive scheme. The calibration of high fidelity parameterized gates and the construction of an efficient circuit compilation scheme that leverages the richer gate set are open problems. In this talk, we present an efficient method for optimizing a selected set of system-wide entangling gates. These gates can be dynamically used online to create short-duration, high-fidelity parametric gates with arbitrary angles, all while demanding minimal calibration resources. To ensure the optimal incorporation of these gates in algorithms, we built a specialized compilation procedure that automatically finds and replaces optimizable patterns in quantum circuits. We demonstrate that our pulse-efficient gate construction and calibration technique enables both a higher fidelity and shorter duration than the standard implementation. This leads to enhanced performance across several key quantum algorithms, including QFT, Trotterized time evolution and QAOA. For instance, when running a 7-qubit MaxCut QAOA, the default circuit execution on a cloud-accessible quantum computer fails to give the correct bit string as the mode of the output distribution while our approach achieves the correct answer with 99% probability. These results signify the importance of both the hardware efficient gates and deterministic error suppression for making quantum devices useful.