Quantum error correction experiments on a superconducting quantum computer with an integrated hardware decoder

Given the fragile nature of qubits, fault tolerant computation will be an important step to reach quantum advantage. The path to full fault tolerance can be broken down into smaller, progressively more challenging quantum error correction experiments (QEC) that indicate quantum computer's ability to protect against errors. We demonstrate the results of experiments run on Rigetti's quantum processors using the surface code and Riverlane's hardware decoder integrated in Rigetti's control stack. The experiments demonstrate suppression of logical errors and fast decoding – two requirements for a successful QEC experiment. We show both the details of experiments as well as the infrastructure built to facilitate QEC experiments and discuss our learnings. Our experiments illustrate the progress of Rigetti's device towards fault tolerant computation. We anticipate that our results and learnings of running QEC experiments on a real device will be pivotal for achieving the next QEC milestones.