Analysis of Imperfect Erasure Detection on Surface Code performance

Due to the possibility of hardware-efficient error correction, recently a lot of effort has been devoted towards designing erasure-biased qubit architectures with the ability to detect dominant errors after every gate operation converting them to erasures. Inevitably however, the experimental implementation of erasure detection will have a finite accuracy. We consider a practical noise model in which an erasure check may return a false negative result, but the subsequent check registers the previously missed erasure. Such delayed erasure detection is not accounted for in existing performance analysis of error correction with erasure qubits. Consequently, in this work we examine the impact of our delayed erasure noise model on the performance of fault-tolerant surface code quantum memory. We assume that an erasure check is applied after every noisy gate in the syndrome extraction circuit. Missed erasures can give rise to correlated errors and moreover, the precise location of these correlations become unknown. We investigate how these effects influence the subthreshold scaling of the logical error rate. Furthermore, we find that when all erasure detections are delayed by a timestep, the threshold decreases to 2.6%, which is nearly half the threshold for perfect erasure detection. Crucially, this threshold of 2.6% is twice the threshold for Pauli errors, implying that erasure qubits are an attractive candidate for easing the requirements of fault-tolerance even when detection is unreliable.