Gate performance statistics from quantum processing units with tens of qubits

ORAL

Abstract

We present an overview of design and fabrication solutions for our scalable superconducting quantum processing units (QPUs). We review the building blocks used in our QPUs including the qubits, tunable coupling elements, readout circuits, and inter-layer connections. Building on the presented solutions, we report the latest performance metrics for simultaneous single- and two-qubit gates and compare the results of standard benchmarks. Finally, we introduce our QPU scaling roadmap from 20 to 54 and 150 data qubits corresponding to more than 400 tunable elements.

* Parts of this work has received support from Business Finland, European Innovation Council, EU Quantum Flagship, and ECSEL/KDT Joint undertaking.

Presenters

  • Johannes Heinsoo

    IQM Quantum Computers

Authors

  • Johannes Heinsoo

    IQM Quantum Computers