From computational materials science to nanoscale device physics

COFFEE_KLATCH · Invited

Abstract

I will outline formal, computational and device level challenges for modeling and simulation of nanoelectronic devices and systems. \textit{Formal} challenges involve developing the basic equations for quantum transport in the presence of strong many-body correlations (Coulomb Blockade), incoherent scattering (phonons) and time-dependent effects at the nano-micro interface (hysteretic switching and random telegraph noise). \textit{Computational} challenges involve translating these equations into quantitative, predictive models, particularly at surfaces and interfaces, where we need practical semi-empirical descriptions with transferable parameters to handle hybrid regions. In addition, we need multiscaling and embedding techniques to merge these models with more detailed ``ab-initio'' descriptions of chemically significant moieties. Finally, \textit{Device} level challenges involve identifying fundamental limits of existing device paradigms, such as molecular FETs, as well as exploring novel device operational principles. I will touch upon the fundamental issues that arise in context of each challenge, and possible means of solving them. I will then apply these ideas to a specific device architecture, namely, an ordered array of quantum dots grown on the surface of a nanoscale silicon transistor. All of the challenges identified above manifest themselves prominently in this geometry that operates at the nano-micro interface. Specifically, I will discuss how the strongly correlated electrons in the nanoscale dots ``talk'' to their weakly interacting macroscopic counterparts, how the interfacial electronic structure captures both long-ranged band correlations and short-ranged chemical correlations, and how the tunable coupling with the localized dot degrees of freedom can lead to novel physics, such as the experimentally observed blocking and unblocking of a nanotube current by correlated interactions between multiple oxide traps.

Authors

  • Avik Ghosh

    Dept. of Electrical and Computer Engineering, University of Virginia