Real-time and Low-latency Quantum Error Correction Experiment Part 1: Rapid Integration of Novel Functionality into the Control System

As quantum computers advance towards demonstrating a universal fault-tolerant logical gate set, implementing scalable and low-latency real-time quantum error correction (QEC) decoding will be crucial. This two-part series presents decoding in real-time with an FPGA decoder integrated into the control system of a superconducting quantum processor. In this first part, we will describe the work of integrating the decoder into Rigetti's control system. We will discuss how this control system, and the soft processor "sequencers" it's built around, affords rapidly creating and exposing new modules to users. With the availability of an embeddable, FPGA-based error decoder created by Riverlane, Rigetti was able to leverage its in-house control system and software to quickly integrate the decoder IP and make real-time error correction available to experimenters. We will discuss how this new feature, along with low-latency result propagation, enabled an experiment with real-time decoded QEC. We will also discuss the creation of a compiler extension that was critical to the speed of making novel FPGA functionality available to users.