Characterizing and benchmarking a superconducting dual-rail cavity qubit processor

Dual-rail qubits using superconducting cavities offer a promising path to realize erasure qubits. In this encoding, the dominant error channel, single-photon loss, can be detected and either postselected or converted into an erasure. Such an architecture leads to lowered requirements for quantum error correction and to improved near-term error-detected algorithms. Realizing such a system requires a toolbox of operations that include state-preparation and measurement, single-qubit gates, two-qubit gates, and erasure-check measurements. In this talk, we introduce a dual-rail qubit processor based on superconducting cavities and show key performance metrics for all operations. Armed with this toolbox, we perform several system-level benchmarks that demonstrate the capability of our dual-rail cavity qubit system.