Abstract
Three-dimensional integration technologies such as flip-chip bonding are a key enabler for large-scale superconducting quantum processors. Modular architectures, in which circuit elements are spread over many chips, can further improve scalability and performance by increasing fabrication yield, enabling the integration of highly diverse elements, and by reducing correlated errors associated with a common qubit substrate. We present our design for a four-qubit, five-chip module where each qubit is on a separate die. Measuring two of the qubits, we analyze the readout performance, finding a mean three-level state-assignment error of 9×10⁻³ in ≤192 ns. We calibrate single-qubit gates and measure simultaneous randomized benchmarking errors of less than 7×10⁻⁴, close to the coherence limit of the qubits. Using a static inter-module coupler featuring galvanic inter-chip transitions, we demonstrate a controlled-Z two-qubit gate in 103 ns with an error of 7×10⁻³ extracted from interleaved randomized benchmarking, also close to the coherence limit.
*The authors acknowledge financial support by the Swiss State Secretariat for Education, Research and Innovation under contract number UeM019-11, by the Intelligence Advanced Research Projects Activity (IARPA) and the Army Research Office, under the Entangled Logical Qubits program and Cooperative Agreement Number W911NF-23-2-0212, by the Baugarten Foundation, by the ETH Zurich Foundation, and by ETH Zurich.The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressed or implied, of IARPA, the Army Research Office, or the U.S. Government. The U.S. Government is authorized to reproduce and distribute reprints for Government purposes notwithstanding any copyright notation herein.
