Testing PSEC5, an 8-Channel, 40 Gs/s waveform digitizing ASIC with a 204 ns long buffer

With the goal of providing picosecond-level timing resolution in large detection systems, we have designed PSEC5, an 8-channel, 40Gs/s waveform-sampling ASIC fabricated in TSMC’s 65nm CMOS process. The distinctive features of the design are the high resolution fast sampling rate and a long buffer. Each channel consists of four fast and one slow switched-capacitor array (SCA), providing sampling windows of 1.6 ns (fast) and 204 ns (slow) respectively. This version of the chip uses an external analog to digital converter (ADC) and phase-locked loop (PLL).

To characterize the performance, we developed two test systems. The preliminary setup, implemented as a chip-on-board (COB), employed an Arduino microcontroller-based interface for functional verification and signal control. The full test system consists of two custom PCBs: a device-under-test (DUT) board for PSEC5 including an external PLL, and a controller board incorporating the external ADC along with the Kria K26 SOM FPGA for high-speed configuration and data readout.

Preliminary results demonstrate stable operation of the on-chip 10.24 GHz VCO and successful communication with the ASIC’s digital control blocks. Both boards were designed in KiCad, with FPGA firmware developed in Vivado. Hopefully more results will be reported.