10.24 GHz Clock Architecture for PSEC6, a 40 GS/s Waveform Sampling in 65nm CMOS

PSEC6 is an 8-channel 40 GS/s multi-hit-capable SCA-based waveform sampling ASIC with the goal of 1-picosecond time resolution.

Each channel has four fast buffers with a 1.6 ns buffer length each and one slow buffer with a204.8 ns buffer length.

1 ps timing resolution simultaneously enables high-SNR Time-of-Flight (TOF) based Positron Emission Tomography (PET) and TOF based particle identification at the few-GeV scale, with potential applications for the EIC and SLAC.

The goal of 1-ps requires a jitter in the sampling clock on the order of 100-fs.

To achieve the required jitter in the VCO in the context of the multi-SCA architecture, we have designed a 10.24-GHz type-III analog Phase-Locked-Loop with a 10.24 GHz LC-VCO and a 40 MHz reference clock, requiring a division ratio of 256 implemented by eight divide-by-two circuits.

The first divider is designed in Current-Mode-Logic (CML), with later stages designed in CMOS logic.

We will present designs and simulations of the CML divider stage, Duty Cycle Corrector (DCC), and Phase Locked Loop (PLL). The PLL works across process variations in schematic simulation and is currently being laid-out.