Impact of CMOS fabrication process tuning on chip performance for CMS HGCAL ECON-D ASIC

The CMS High-Granularity Calorimeter (HGCAL) upgrade will replace the existing endcap calorimeters to meet HL-LHC conditions, providing an imaging calorimeter with over six million channels. To sustain physics performance at high pileup while meeting challenging power and bandwidth requirements, CMS has developed two novel Endcap Concentrator (ECON) ASICs: ECON-T for the 40 MHz trigger path and ECON-D for the trigger-accepted event data path (~750 kHz). Implemented in 65 nm CMOS, the devices are radiation-tolerant to 200 Mrad and operate at <2.5 mW per channel. Full-functionality prototypes were produced and characterized in 2021–2023, followed by an initial engineering run of 33k ASICs in 2024. Radiation testing of ECON-D from the engineering run revealed read errors in the on-chip SRAMs for a non-negligible subset of devices. Further investigation indicated that SRAM robustness is sensitive to fabrication-process parameters. To quantify and mitigate this sensitivity, a dedicated 2025 production of wafers was undertaken with a range of doping concentrations designed to tune the underlying transistor threshold voltage by 0%, 5%, 10%, and 15% from nominal. We present the measurements of ECON-D SRAM performance and power consumption for these four varieties of CMOS process.