Device benchmarking of utility scale quantum processors

As modern quantum processors have pushed to larger scales and lower error rates, the task of low-level device benchmarking has grown in complexity. While there are established protocols to report simple metrics such as qubit coherence and error rates from randomized benchmarking (RB), these cannot adequately characterize devices at scale and track hardware improvements. For example, RB reports error rates without circuit structure or crosstalk. Furthermore, modern devices have added features such as enhanced gatesets involving non-Clifford “fractional” two-qubit gates and feedforward operations (dynamic circuits). Therefore, to characterize our devices, we have developed a toolbox of methods to enable full coverage. While we start with standard RB, we build on that with purity RB, then layer fidelity (RB in structured layers) [1,2], Bell tests for fractional and dynamic circuits and RB protocols that include mid-circuit measurement [3] and dynamic circuits [4].

In this talk, we will discuss the principles behind each protocol, demonstrate how they enable us to build a full device health view, and share data from recently deployed systems highlighting the progress achieved across successive system generations.

[1] arXiv:2311.05933 [2] arXiv:2510.16915 [3] arXiv:2207.04836 [4] arXiv:2408.07677