Hardware-Efficient Erasure Qubits With Superconducting Qutrits (1/2)

Quantum error correction using erasure qubits offers higher fault-tolerance thresholds and better scaling by converting certain errors into detectable erasures, but current implementations using dual-rail approaches require a sizeable hardware overhead. In Part I, we demonstrate a hardware-efficient erasure qubit scheme that employs a single qutrit rather than two qubits or modes. The logical states |0> and |1> are encoded in the ground and second excited state, while decay from |1> to an intermediate ∣e⟩ state produces a detectable erasure. Detection is performed via an ancilla qubit using a two-qutrit SWAP gate between ∣eg⟩ and ∣0f⟩ states, based on a four-wave mixing process. This approach, independent of the ancilla transition frequency, efficiently identifies amplitude decay events, enabling a resource-efficient pathway toward scalable, fault-tolerant quantum error correction with erasure qubits.