Hardware-Efficient Erasure Qubits With Superconducting Qutrits (2/2)

Quantum error correction using erasure qubits offers higher fault-tolerance thresholds and better scaling by converting certain errors into detectable erasures, but current implementations using dual-rail approaches require a sizeable hardware overhead. In Part II, we demonstrate logical lifetime of erasure qubit exceeding 300 µs, post-selected with repeated erasure detection—five times longer than the T1 time of the bare transmon qubit. Coherence times beyond 200µs are achieved using dynamical decoupling and spin-locking pulse sequences. Single-qubit gate operations reach average fidelities as high as 0.9995. By reusing a single ancilla (erasure detection) qubit for parity checks, we generate a Bell state between two erasure qubits with 89% fidelity, verified through quantum state tomography. These results highlight the potential of erasure qubits for extending coherence and enabling scalable, fault-tolerant quantum error correction.